Title :
Highly stable 65 nm node (CMOS5) 0.56 /spl mu/m/sup 2/ SRAM cell design for very low operation voltage
Author :
Kanda, M. ; Morifuji, E. ; Nishigoori, M. ; Fujimoto, Y. ; Uematsu, M. ; Takahashi, K. ; Tsuno, H. ; Okano, K. ; Matsuda, S. ; Oyamatsu, H. ; Takahashi, H. ; Nagashima, N. ; Yamada, S. ; Noguchi, T. ; Okamoto, Y. ; Kakumu, M.
Author_Institution :
Semicond. Co., Toshiba Corp., Yokohama, Japan
Abstract :
We show very high density embedded 6T-SRAM cell of 0.56 /spl mu/m/sup 2/. This is the smallest value reported so far. Developed embedded SRAM cell achieves adequate SNM of 90 mV at 0.6 V on high performance 65 nm SoC platform (CMOS5).
Keywords :
CMOS memory circuits; SRAM chips; monolithic integrated circuits; semiconductor device noise; system-on-chip; 0.6 V; 65 nm; 90 mV; CMOS; SRAM cell design; density; operation voltage; static noise margin; system-on-chip platform; CMOS technology; Contacts; Electrodes; Energy consumption; Gate leakage; Joining processes; Low voltage; Process design; Random access memory; Stability;
Conference_Titel :
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-033-X
DOI :
10.1109/VLSIT.2003.1221062
