A novel Dynamic Voltage Scaling technique for low-power FPGA systems

Dynamic Voltage Scaling (DVS) has been a key technique in exploiting the hardware characteristics of processors to reduce energy dissipation by lowering the supply voltage and operating frequency. As applications become increasingly sophisticated and processing power increases, the most serious limitation on these devices is the available battery life. This paper presents a low-power FPGA system with multiple supply voltage. The critical path of data arrival of the asynchronous architecture can be easily detected by detecting the change of the data´s phase. Logic blocks on the non-critical path are autonomously switched to a lower supply voltage to reduce the power consumption. A novel DVS algorithm is presented, so that supply voltage to each logic block is made self-adaptive to the workload and data path, so as to minimize the power consumption without system performance degradation and been demonstrated using the FPGA system, a digitally adjustable DC-DC regulator and a power aware operating system. The simulations results show that up to 60% less energy is consumed with DVS than with a fixed supply voltage.