Design guideline of HfSiON gate dielectrics for 65 nm CMOS generation

Characteristics of sub-100 nm CMOSFETs with HfSiON gate dielectrics with various Hf concentrations (/spl Cscr/;/sub Hf/) have been investigated, and the design guideline to obtain the superior device performance is presented for the first time. It is found that MOSFETs with lower /spl Cscr/;/sub Hf/ results in higher drive current due to lower parasitic resistance (R/sub para/) for the same effective oxide thickness (EOT). Therefore, /spl Cscr/;/sub Hf/ should be kept low in so far as it meets the /spl Iscr/;/sub g/ target in order to obtain good MOSFET performance. It is demonstrated that 50 nm gate CMOSFETs with optimized HfSiON show high drive current of 650 /spl mu/A//spl mu/m and 250 /spl mu/A//spl mu/m for n-and p-MOSFET, respectively, with low gate leakage current (/spl Iscr/;/sub g/) of 0.3 A/cm/sup 2/ while maintaining the thermal stability up to 1050/spl deg/C. This performance exceeds reported value of sub-100 nm CMOSFET with high-k materials.