Evaluating macro placement in an SoC block based on a congestion estimate

Modern SoC designs are increasingly constrained by routing resources due to factors such as cell density, signal integrity requirements, antenna rules, and extensive use of predesigned macro blocks with route blockages. The positioning of macros has significant impact on the overall routability of a design. Lack of early congestion analysis techniques necessitates multiple iterations of place and route to identify a satisfactory macro placement, consuming substantial time and an enormous amount of computational resources. The proposed approach helps designers identify congestion issues related to macro placement early on and take steps to resolve them upfront. Experimental results suggest good correlation between the proposed method and detailed route results, with obvious advantages.