3D TFT-SONOS memory cell for ultra-high density file storage applications

Author

Walker, A.J. ; Nallamothu, S. ; Chen, E.-H. ; Mahajani, M. ; Herner, S.B. ; Clark, M. ; Cleeves, J.M. ; Dunton, S.V. ; Eckert, V.L. ; Gu, J. ; Hu, S. ; Knall, J. ; Konevecki, M. ; Petti, C. ; Radigan, S. ; Raghuram, U. ; Vienna, J. ; Vyvoda, M.A.

Author_Institution

Matrix Semicond. Inc., Santa Clara, CA, USA

fYear

2003

fDate

10-12 June 2003

Firstpage

29

Lastpage

30

Abstract

For the first time, a scalable, low power, deep-submicron TFT-SONOS (Thin-Film Transistor Silicon-Oxide-Nitride-Oxide-Silicon) memory cell is described with characteristics rivaling those of single crystal devices (>10/sup 6/ cycles, /spl sim/1.6 V window after 10 years on cycled cell at 85 C) showing the promise of 3D integration and ultra-small cell footprints. The ability to vertically stack device layers enables the current memory density record of /spl sim/200 Mbyte/cm/sup 2/, set by 90 nm NAND, to be surpassed.

Keywords

NAND circuits; elemental semiconductors; field effect memory circuits; semiconductor thin films; silicon; silicon compounds; thin film transistors; 1.6 V; 3D TFT silicon oxide nitride oxide silicon memory cell; 3D integration; 90 nm; NAND; Si-SiN-Si; current memory density record; single crystal devices; ultra high density file storage; ultra small cell footprints; vertically stack device layers; Costs; Fabrication; Hafnium; Nonvolatile memory; SONOS devices; Silicon; Thin film transistors; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221070

Filename

1221070