DocumentCode
1866594
Title
ArF lithography technologies for 65 nm-node CMOS (CMOS5) with 30 nm logic gate and high density embedded memories
Author
Hashimoto, K. ; Uesawa, F. ; Takahata, K. ; Kikuchi, K. ; Kanai, H. ; Shimizu, H. ; Shiobara, E. ; Takeuchi, K. ; Endo, A. ; Harakawa, H. ; Mimotogi, S.
Author_Institution
Semicond. Co., Toshiba Corp., Yokohama, Japan
fYear
2003
fDate
10-12 June 2003
Firstpage
45
Lastpage
46
Abstract
In this paper ArF lithography technology for 65nm-node CMOS with 30nm logic gate and high density embedded memories have been demonstrated. ArF step-and-scan exposure systems with 0.75NA are available under accurate lithography design with level specific focus and does error budgets. Also,the process steps with two kinds of lithography are implemented to fabricate GC pattern.
Keywords
CMOS logic circuits; DRAM chips; embedded systems; lithography; logic gates; semiconductor technology; 30 nm; 65 micron; ArF; ArF lithography technology; CMOS; high density embedded memories; logic gate; CMOS logic circuits; CMOS process; CMOS technology; Etching; Fabrication; Focusing; Lithography; Logic gates; Random access memory; Resists;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-033-X
Type
conf
DOI
10.1109/VLSIT.2003.1221078
Filename
1221078
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