Author :
Katsumata, R. ; Tsuda, N. ; Idebuchi, J. ; Kondo, M. ; Aoki, N. ; Ito, S. ; Yahashi, K. ; Satonaka, T. ; Morikado, M. ; Kito, M. ; Kido, M. ; Tanaka, T. ; Aochi, H. ; Hamamoto, T.
Abstract :
Fin gate array transistor (Fin-Array-FET) fabricated on bulk silicon substrate is applied to the DRAM cell with the deep trench (DT) capacitor. Fin-Array-FET is designed for the 130 nm technology node and beyond by using the 3-D device simulator (HyDeLEOS) and process simulator (HySyProS). It is demonstrated that the on-current of Fin-Array-FET is 62 /spl mu/A/cell that is about 1.7 times as much as conventional planer array FET, keeping the off-current 0.1 fA/cell. It is also demonstrated that Fin-Array-FET on bulk silicon substrate can relieve of the retention degradation because the channel boron doping can be reduced to more than one order compared to the conventional planar array FET.
Keywords :
DRAM chips; capacitors; field effect transistors; semiconductor device models; 0.1 fA; 100 nm; 130 nm; 3D device simulator; 3D process simulator; 62 muA; Si:B; bulk silicon substrate; channel boron doping; deep trench capacitor DRAM; fin array FET; Boron; Capacitors; Degradation; Doping; Electrodes; MOSFETs; Random access memory; Silicon; Threshold voltage; Transistors;
