A functional 0.69 /spl mu/m/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

Author

Arnaud, F. ; Boeuf, F. ; Salvetti, F. ; Lenoble, D. ; Wacquant, F. ; Regnier, C. ; Morin, P. ; Emonet, N. ; Denis, E. ; Oberlin, J.C. ; Ceccarelli, D. ; Vannier, P. ; Imbert, G. ; Sicard, A. ; Perrot, C. ; Belmont, O. ; Guilmeau, I. ; Sassoulas, P.O. ; De

Author_Institution

STMicroelectron., Crolles, France

fYear

2003

fDate

10-12 June 2003

Firstpage

65

Lastpage

66

Abstract

This work highlights a 65 nm CMOS technology platform for low power and general-purpose applications. A 6-T SRAM cell size of 0.69 /spl mu/m/sup 2/ with a 45 nm gate length is demonstrated. Electrical data of functional SRAM bit-cell is presented at V/sub dd/=0.9 Volt using a conventional nitrided gate oxide dielectric. A comparison between offset spacer and PLAsma Doping (PLAD) is made for the transistor characteristics with very promising V/sub th/-L/sub d/ and V/sub th/-W/sub d/ profiles measured. Lithography employed a combination of both optical lithography and e-beam imaging. The BEOL integration used a conventional low K dielectric with copper metallization.

Keywords

CMOS integrated circuits; MOSFET; SRAM chips; copper; integrated circuit metallisation; photolithography; 45 nm; 65 nm; CMOS platform; Cu; copper metallization; electron beam imaging; embedded SRAM bit cell; lithography; nitrided gate oxide dielectrics; optical lithography; transistor properties; CMOS technology; Copper; Dielectric measurements; Doping profiles; Lithography; Metallization; Optical imaging; Plasma measurements; Plasma properties; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221088

Filename

1221088