Title :
Robust process integration of 0.78 /spl mu/m/sup 2/ embedded SRAM with NiSi gate and low-K Cu interconnect for 90 nm SoC applications
Author :
Kim, Y.W. ; Ahn, J.H. ; Park, T.S. ; Oh, C.B. ; Lee, K.T. ; Kang, H.S. ; Lee, D.H. ; Ko, Y.G. ; Cheong, K.S. ; Jun, J.W. ; Liu, S.H. ; Kim, J. ; Nam, J.L. ; Ha, S.R. ; Park, J.B. ; Song, S.A. ; Suh, K.P.
Author_Institution :
Technol. Dev., Samsung Electron., Kyunggi-Do, South Korea
Abstract :
The smallest high density embedded 0.78 /spl mu/m/sup 2/ 6T-SRAM cell for high performance 90 nm SoC applications was successively integrated by using leading edge technologies such as 193 nm ArF lithography, 1.2 nm gate oxide, 50 nm transistor and Cu dual damascene with low-K dielectric. Fully working for SRAM shows the SNM value above 200 mV. Device current of 870 /spl mu/A//spl mu/m and 390 /spl mu/A//spl mu/m for NMOS and PMOS respectively is achieved at 1.0 V operation. Reliability life time on hot carrier immunity shows more than 10 years.
Keywords :
MOSFET; SRAM chips; copper; dielectric materials; integrated circuit interconnections; integrated circuit reliability; lithography; nickel compounds; system-on-chip; 1 V; 1.2 nm; 10 year; 193 nm; 50 nm; 90 nm; ArF lithography; Cu; NMOS; NiSi; NiSi gate; PMOS; SoC; embedded SRAM; gate oxide; hot carrier immunity; low-K Cu interconnect; reliability life time; robust process integration; transistor; Etching; Hot carriers; Implants; Large scale integration; Lithography; Logic devices; MOS devices; Nickel; Random access memory; Robustness;
Conference_Titel :
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-033-X
DOI :
10.1109/VLSIT.2003.1221090
