A highly manufacturable 110 nm EDRAM process with Al/sub 2/O/sub 3/ stack MIM capacitor for cost effective high density, high speed, low voltage ASIC memory applications

Author

Fishburn, F. ; Kauffman, R. ; Lane, R. ; McDaniel, T. ; Schofield, K. ; Southwick, S. ; Turi, R. ; Hongmei Wang

Author_Institution

Process R&D Center, Micron Technol., Boise, ID, USA

fYear

2003

fDate

10-12 June 2003

Firstpage

75

Lastpage

76

Abstract

A highly manufacturable 110 nm Embedded DRAM technology with stack Al/sub 2/O/sub 3/ MIM capacitor has been demonstrated successfully for the first time. High-density DRAM core with 0.1 /spl mu/m/sup 2/ cell size and high performance logic circuits have been realized at the same time by separation of the gate pattern at memory cell and peripheral logic region. Low temperature BDL process, highly reliable Al/sub 2/O/sub 3/ MIM capacitors have been developed to control process temperature. DRAM cell performance has been improved by introducing tungsten wordline, CoSi/sub 2/ plug and tungsten bitline. 7 levels Cu and CVD-OSG low-k material have been implemented to satisfy the requirement of high performance logic circuits design.

Keywords

DRAM chips; MIM devices; alumina; application specific integrated circuits; capacitors; dielectric materials; 110 nm; Al/sub 2/O/sub 3/; CVD; MIM capacitor; application specific integrated circuit memory applications; density; embedded DRAM process; gate pattern; high speed; logic circuits design; low voltage; low voltage ASIC memory applications; memory cell; tungsten bitline; tungsten wordline; Application specific integrated circuits; Costs; Logic circuits; Low voltage; MIM capacitors; Manufacturing processes; Plugs; Random access memory; Temperature; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221093

Filename

1221093