A fabless company´s perspective on large die Chip Package Interaction (CPI) challenges

FPGAs continue to evolve at most advanced semiconductor technology nodes, and in larger die and package form factors to meet the increasing demands for performance from high end systems. Scaling of the low-k dielectric material in the die at these nodes poses a challenge, not only for process integration, but also for Chip Package Interaction (CPI) reliability. Here we review some of the major concerns with large die CPI reliability in light of this relentless march towards lower-k material. We also propose a need for collaboration across multiple parties (Fab, Component Supplier, Assembly House, Board Supplier, System Designer, and End Customer) in order to successfully meet performance goals without sacrificing reliability needs for the system.