Title :
A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer
Author :
Hornung, B. ; Khamankar, R. ; Niimi, H. ; Goodwin, M. ; Robertson, L. ; Miles, D. ; Kirkpatrick, B. ; AlShareef, H. ; Varghese, A. ; Bevan, M. ; Nicollian, P. ; Chidambaram, P.R. ; Chakravarthi, S. ; Gurba, A. ; Zhang, X. ; Blatchford, J. ; Smith, B. ; Lu
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
A 90 nm logic technology is presented featuring an aggressively scaled 37 nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with different extension offsets for NMDD and PMDD implants, which enables independent optimization of short channel effects, parasitic capacitance and drive current. The gate dielectric meets reliability requirements at 1.2 V operation. The technology includes a standard Vt (SVt) transistor, low Vt (LVt) transistor and 1.5 V IO transistor with l00 nm gate length and dual plasma nitrided gate dielectric.
Keywords :
MOSFET; capacitance; semiconductor device reliability; 1.2 V; 1.3 nm; 1.5 V; 100 nm; 37 nm; 90 nm; NMOS transistors; PMOS transistors; dielectric offset spacer; differential offset spacer; drive current; dual plasma nitrided gate dielectrics; gate length; logic technology; low voltage transistor; optimization; parasitic capacitance; reliability; short channel effects; standard voltage transistor; CMOS technology; Dielectrics; Gate leakage; Implants; Logic; MOS devices; MOSFETs; Parasitic capacitance; Plasma devices; Space technology;
Conference_Titel :
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-033-X
DOI :
10.1109/VLSIT.2003.1221098
