Title :
SILC and gate oxide breakdown characterization of 22nm tri-gate technology
Author :
Ramey, S. ; Hicks, J.
Author_Institution :
Logic Technol. Dev. Quality & Reliability, Intel Corp., Hillsboro, OR, USA
Abstract :
The SILC behavior in 22nm tri-gate devices is reduced compared to 32nm planar devices due to gate optimization and benefits from the tri-gate architecture. A product risk assessment method is presented that compares SILC to hard breakdown. The technology is fully characterized for NMOS, PMOS, stress voltage and polarity, with data indicating that SILC is low risk for product operation.
Keywords :
MOS integrated circuits; semiconductor device breakdown; NMOS; PMOS; SILC behavior; gate optimization; gate oxide breakdown characterization; planar devices; product risk assessment method; size 22 nm; stress induced leakage current; stress polarity; stress voltage; trigate architecture; Electric breakdown; Gate leakage; Logic gates; MOS devices; Monitoring; Stress; FinFET; SILC; TDDB; reliability; tri-gate;
Conference_Titel :
Reliability Physics Symposium, 2014 IEEE International
Conference_Location :
Waikoloa, HI
DOI :
10.1109/IRPS.2014.6860621
