Title :
Performance of 70 nm strained-silicon CMOS devices
Author :
Hwang, J.R. ; Ho, J.H. ; Ting, S.M. ; Chen, T.P. ; Hsieh, Y.S. ; Huang, C.C. ; Chiang, Y.Y. ; Lee, H.K. ; Ariel Liu ; Shen, T.M. ; Braithwaite, G. ; Currie, M. ; Gerrish, N. ; Hammond, R. ; Lochtefeld, A. ; Singaporewala, F. ; Bulsara, M. ; Xiang, Q. ; Li
Author_Institution :
Central Res. & Dev. Div., UMC, Hsinchu, Taiwan
Abstract :
An 86% electron mobility improvement and over 20% I/sub dn-sat/ enhancement were demonstrated for a 70 nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained-Si process delivered 95% higher inverter peak-current and a 2.2 ps reduction in ring oscillator delay for the same drive current. Strained and bulk CMOS featured equivalent gate leakage through a 16 /spl Aring/ nitrided oxide, which remained the dominant leakage source despite dislocation-induced junction leakage observed on strained-Si wafers. Self-heating of strained-Si CMOS due to the low thermal conductivity SiGe virtual substrate reduces I/sub dn-sat/ by 7% during DC operation.
Keywords :
MOSFET; electron mobility; elemental semiconductors; leakage currents; silicon; 16 /spl Aring/; 2.2 Ps; 70 nm; Si; SiGe; SiGe virtual substrates; dislocation-induced junction; electron mobility; leakage current; ring oscillator delay; strained-silicon CMOS devices; thermal conductivity; CMOS process; CMOS technology; Electron mobility; Germanium silicon alloys; Inverters; MOS devices; Ring oscillators; Silicides; Silicon germanium; Thermal conductivity;
Conference_Titel :
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-033-X
DOI :
10.1109/VLSIT.2003.1221107
