Title :
Integration of Cu/low-k dual-damascene interconnects with a porous PAE/SiOC hybrid structure for 65 nm-node high performance eDRAM
Author :
Kanamura, R. ; Ohoka, Y. ; Fukasawa, M. ; Tabuchi, K. ; Nagahata, K. ; Shibuki, S. ; Muramatsu, M. ; Miyajima, H. ; Usui, T. ; Kajita, A. ; Shibata, H. ; Kadomura, S.
Author_Institution :
Technol. Dev. Div., Sony Corp., Kanagawa, Japan
Abstract :
Porous PAE/SiOC(k2.5)/SiC(k3.5) hybrid dual damascene (DD) interconnects have been successfully integrated for a 65 nm-node high performance embedded DRAM. The hybrid DD structure was fabricated by applying a triple hard mask (THM) process-for the first time-that resulted in excellent yield of 1 M via chains. The THM process produces a well-controlled DD profile without complexity of process integration. The porosity of the porous PAE was optimized to enhance the mechanical strength and thus prevent process-induced damages. The hybrid DD interconnects with the porous PAE and the second-generation SiOC/SiC (k2.5/3.5) dielectrics resulted in no degradation of line-to-line leakage current and elimination of stress-induced voiding. It is concluded that this hybrid DD interconnects fabricated by the THM process is the most promising one to satisfy all the requirements for 65 nm-node eDRAM.
Keywords :
DRAM chips; copper; dielectric materials; integrated circuit interconnections; leakage currents; porosity; porous materials; silicon compounds; 65 nm; Cu; Cu/low-k dual-damascene interconnection technology; SiOC-SiC; embedded DRAM; leakage current; porosity; porous PAE/SiOC/SiC hybrid structure; triple hard mask; Capacitance; Degradation; Dielectrics; Etching; Fabrication; Leakage current; Random access memory; Silicon carbide; Silicon compounds; Wiring;
Conference_Titel :
VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-033-X
DOI :
10.1109/VLSIT.2003.1221109
