High performance/reliability Cu interconnect with selective CoWP cap

Author

Ko, T. ; Chang, C.L. ; Chou, S.W. ; Lin, M.W. ; Lin, C.J. ; Shih, C.H. ; Su, H.W. ; Tsai, M.H. ; Shue, W.S. ; Liang, M.S.

Author_Institution

Taiwan Semicond. Manuf. Co. Ltd., Hsin-Chu, Taiwan

fYear

2003

fDate

10-12 June 2003

Firstpage

109

Lastpage

110

Abstract

In this work, a selective CoWP metal cap was employed after Cu CMP process for replacing conventional dielectric cap layer platform. A 5% reduction in RC delay was demonstrated for this new approach. The CoWP cap layer improves the interface between Cu and dielectric layer which reduces the Cu surface migration. EM for both via and trench shows more than 10X improvement. With optimized thickness and deposited process, 100% yield of line to line leakages, via chain Rc, and metal line Rs can be achieved. A semi-quantitative model was employed to determine surface migration dominating EM failure.

Keywords

cobalt alloys; copper; dielectric thin films; integrated circuit interconnections; integrated circuit reliability; phosphorus alloys; surface diffusion; tungsten alloys; CoWP; Cu; Cu interconnect; Cu surface migration; dielectric cap layer; line leakage; reliability; semi quantitative model; Copper; Current measurement; Delay; Dielectric measurements; Equations; Leakage current; Paper technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221110

Filename

1221110