Accurate modeling method for deep sub-micron Cu interconnect

This paper newly proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density are fully incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow which features correlating cross-section observation and resistance measurement to obtain the parameter values. We have extracted the model parameters for 0.15 /spl mu/m CMOS using this method and confirmed that 10% /spl tau/pd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. This is the first time that the practical and accurate modeling methodology for layout pattern sensitive Cu Interconnect is ever reported.