Highest frequency optimization of VLSI by a novel clock skew scheduling scheme

The paper proposes a novel clock skew scheduling scheme, which is used to improve the highest frequency of VLSI (Very Large Scale Integrated Circuits) and has higher efficiency than the traditional scheme. To reduce the n of flow iterations, the feature of physical-optimizing-potential is embedded. A lookup table about the physical distance and the optimizing potential is generated before performing the clock skew scheduling algorithm. By this table, fake critical paths are removed, that relieves the stress of the clock skew algorithm and makes the optimizing more efficient. Besides, to make sure the optimizing potential can be realized, some particular physical constraints should be set. Genetic algorithm is adopted to find a minimum subset which includes the paths must be constrained. Experiments on ARM1136J-FS show that the highest frequency increases 13% and the time consumption is almost halved compared to the traditional.