Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling

Author

Fu-Liang Yang ; Hou-Yu Chen ; Chien-Chao Huang ; Chun-Hu Ge ; Ke-Wei Su ; Cheng-Chuan Huang ; Chang-Yun Chang ; Da-Wen Lin ; Chung-Cheng Wu ; Jaw-Kang Ho ; Wen-Chin Lee ; Yee-Chia Yeo ; Diaz, C.H. ; Mong-Song Liang ; Sun, J.Y.-C. ; Chenming Hu

Author_Institution

Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan

fYear

2003

fDate

10-12 June 2003

Firstpage

137

Lastpage

138

Abstract

A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

Keywords

MOSFET; silicon; silicon-on-insulator; 65 nm; CMOS scaling; FIP-SOI (finFET/FD/PD-SOI); NMOS; SOI technology; channel strain; strained silicon; Capacitive sensors; Circuits; Dielectric substrates; FinFETs; Immune system; Isolation technology; Manufacturing processes; Scalability; Semiconductor device manufacture; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-033-X

Type

conf

DOI

10.1109/VLSIT.2003.1221123

Filename

1221123