Design of a low leakage ESD clamp for high voltage supply in 65nm CMOS technology

System on Chip (SOC) designs in 65nm and beyond CMOS processes have the need to support higher voltage power supply domains in addition to the more traditional core and I/O voltages. In this work a new supply clamp architecture is proposed which ensures a reliable low leakage performance at the Higher supply voltages (5.0V for 65nm). The clamp´s turn-on characteristics spans the full duration of the actual ESD events making it fully capable to effectively protect the sensitive devices in the 5V core circuit. The low leakage aspect of the supply clamp is demonstrated with the help of high temperature measurements.