Highly manufacturable sub-50 nm high performance CMOSFET using real damascene gate process

We demonstrate highly manufacturable sub-50 nm CMOSFETs using ´real´ damascene gate process without dummy gate formation, which has structural merits in scaling resulting from locally implanted channel. The fabricated sub-50 nm CMOSFETs show the excellent suppression of short channel effect due to the locally implanted channel and the outstanding current drivability, 810 /spl mu/A//spl mu/m for nMOS and 424 /spl mu/A//spl mu/m for pMOS at V/sub DD/=1.0 V and I/sub OFF/=100 nA//spl mu/m. In particular, the pMOS performance is comparable to the state-of-the-art result.