A fast computable delay model for subthreshold circuit

The subthreshold circuit is a promising ultra-low-power solution for such applications that don´t require high speed but are extremely power-stringent. The characteristic of the current under subthreshold voltage is different from the normal domain. A delay model is essential to predict the performance, analyze the variation impacts and optimize the design. This paper proposes a fast computable delay model for subthreshold circuit. The model requires a few parameters and is easy to calculate quickly. A 32-stage inverter-chain designed by 180nm process is used to verify the model and the calculated results indicate that the model error is less than 10% compared with HSPICE.