Voltage up level shifter with improved performance and reduced power

In Ultra Deep Sub Micron technology nodes, particularly 45nm and below, multiple power supplies are needed to achieve optimum performance. In such SoC´s, level shifters play an important role in translating the signals from one voltage level to another. The conventional level shifters suffer from the contention between the pull up and pull down transistors which leads to the increase in delay and the power consumption, so the existing techniques are unable to address the requirement of wide range of voltage translation at lower core voltages below 1V. In this paper a new voltage up level shifter has been proposed and designed for up shifting the signal levels for a wide range of voltage levels. This circuit consists of level shifter block and reference voltage generation circuit, which generates a constant voltage depending up on the ratio between pre charge rate and discharge rate to avoid the contention between pull up and pull down transistors of level shifter block. It results in faster transition and less power compared to earlier level shifters. The proposed circuit is designed in 45nm CMOS technology using POWERSPICE, consumes only 89.4nw power and gives an average delay of 70ps at Vin = 0.45V, VDDH = 1.05V while occupying an area of 1.67um².