A new gate pattern measurement for evaluating the BTI degradation in circuit conditions

In this paper, we develop a new “recovery free” measurement technique able to apply arbitrary NBTI stress patterns of `1´ & `0´ on the gate of the transistor. This technique is very useful to evaluate the BTI degradation seen by the device in circuit conditions. With this method, it is shown that the NBTI shift does not depend on the bit arrangement within a sequence for bit length <;1μs but only on the overall circuit activity. Such a result validates the standard approach based on regular AC stress to address NBTI concern at circuit level. Furthermore, all the revisited results obtained with our new measurement technique are successfully modeled using a dedicated numerical RC model. It gives new insights on the physical mechanisms responsible for NBTI in advanced nodes.