HCI/BTI coupled model: The path for accurate and predictive reliability simulations

The standard qualification of CMOS Wafer Level Reliability by manufacturers consists in qualifying BTI mechanism from one side and HCI from another side independently. Their respective degradation are then assumed to be additive. Here, we study the interaction between both mechanisms through alternative stress sequences at device level and also in ring oscillators. Interaction formalism is proposed and implemented in Design-in-Reliability simulation framework. While two ageing mechanisms co-exist and are interacting, we consider the origin of mechanisms (non-conducting HCI, low-E HCI...) and quantify the weight of coupling. We also point out that without this interaction consideration in Design-in-Reliability simulation, results are significantly inaccurate and pessimistic. Finally, we present degradation results for a large amount of standard cell RO-based at package level, at different stress/time conditions and conclude that this feature of simulation is a must have in logic Design Platform characterization in order to avoid over-estimation of timing degradation.