Title :
Adaptive parallel system as the high performance parallel architecture
Author :
Kim, Jeong-Min ; Kim, Youngsik ; Kim, Shin-Dug ; Han, Tack-Don ; Yang, Sung-Bong
Author_Institution :
Parallel Process. Syst. Lab., Yonsei Univ., Seoul, South Korea
fDate :
28 Apr-2 May 1997
Abstract :
An approach for designing a hybrid parallel system that can perform adaptively for different types of parallelism is presented. An adaptive parallel system (APS) is proposed to attain this goal. The APS is constructed by integrating tightly two different types of parallel architectures, i.e., a multiprocessor system and a memory based processor array (MPA), into a single machine. The multiprocessor and the MPA can execute medium to coarse grain parallelism and fine grain data parallelism optimally. One important feature in the APS is that the programming interface is the same as the usual subroutine call mechanism to execute data parallel code on the MPA. Thus the existence of the MPA is transparent to the programmers. This research concerns the design of an underlying base architecture that can be optimally executed for a broad range of applications, from coarse grain to fine grain parallelism. Also the performance model is provided for fair comparison with other approaches. It turns out that the proposed APS can provide significant performance improvement and cost effectiveness for highly parallel applications having a mixed set of parallelisms
Keywords :
application program interfaces; cost-benefit analysis; multiprocessing systems; parallel architectures; parallel programming; performance evaluation; subroutines; adaptive parallel system; coarse grain parallelism; cost effectiveness; fine grain data parallelism; high performance parallel architecture; hybrid parallel system design; medium grain parallelism; memory based processor array; multiprocessor system; performance model; programming interface; subroutine call; Adaptive systems; Algorithms; Computer science; Costs; Laboratories; Multiprocessing systems; Parallel architectures; Parallel processing; Parallel programming; Performance evaluation;
Conference_Titel :
High Performance Computing on the Information Superhighway, 1997. HPC Asia '97
Conference_Location :
Seoul
Print_ISBN :
0-8186-7901-8
DOI :
10.1109/HPC.1997.592208