• DocumentCode
    1868329
  • Title

    Clock generation and distribution for the third generation Itanium/spl reg/ processor

  • Author

    Tam, S. ; Desai, U. ; Limaye, R.

  • Author_Institution
    Intel Corp., Santa Clara, CA, USA
  • fYear
    2003
  • fDate
    12-14 June 2003
  • Firstpage
    9
  • Lastpage
    12
  • Abstract
    The clock generation and distribution system for the third generation Itanium/spl reg/ processor operates at 1.5 GHz with a skew of 24 ps. Clock optimization fuses enable post-silicon speed path balancing for higher performance.
  • Keywords
    CMOS integrated circuits; clocks; elemental semiconductors; microprocessor chips; silicon; 1.5 GHz; 24 ps; Itanium/spl reg/ processor; clock generation; clock optimization; post silicon speed path; Circuits; Clocks; Copper; Feedback; Frequency; Fuses; Mesh generation; Phase locked loops; Signal generators; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    4-89114-034-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.2003.1221148
  • Filename
    1221148
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1868329