Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Author

Chun-Yu Lin ; Pin-Hsin Chang ; Rong-Kun Chang ; Ming-Dou Ker ; Wen-Tai Wang

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Normal Univ., Taipei, Taiwan

fYear

2015

fDate

June 29 2015-July 2 2015

Firstpage

255

Lastpage

258

Abstract

A vertical silicon-controlled rectifier (SCR) structure utilizing ESD implantation layer was proposed and implemented in nanoscale CMOS technology. Compared with the traditional SCR structure, the proposed structure has lower trigger voltage and high enough ESD protection capability. Therefore, the proposed structure was suitable for ESD protection in nanoscale CMOS process.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; nanotechnology; thyristors; ESD implantation layer; nanoscale CMOS technology; on-chip ESD protection; trigger voltage; vertical SCR structure; vertical silicon-controlled rectifier structure; CMOS integrated circuits; CMOS technology; Electrostatic discharges; Logic gates; Nanoscale devices; Thyristors;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/IPFA.2015.7224380

Filename

7224380

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1868409