Title :
3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits
Author :
Jonghae Kim ; Plouchart, J.-O. ; Zamdmer, N. ; Sherony, M. ; Liang-Hung Lu ; Yue Tan ; Meeyoung Yoon ; Jenkins, K.A. ; Kumar, M. ; Ray, A. ; Wagner, L.
Author_Institution :
Semicond. Res. & Dev. Center, IBM, Hopewell Junction, NY, USA
Abstract :
This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.
Keywords :
CMOS integrated circuits; MIM devices; UHF devices; capacitors; radiofrequency integrated circuits; silicon-on-insulator; 0.12 micron; 1 GHz; 20 pF; 3-dimensional vertical parallel plate capacitors; SOI CMOS technology; capacitance density; integrated radio frequency circuits; CMOS technology; Capacitance; Conductivity; Geometry; Integrated circuit interconnections; Integrated circuit technology; MIM capacitors; Metal-insulator structures; Radio frequency; Research and development;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221153
