DocumentCode
1868599
Title
A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface using novel eye-tracking method
Author
Saito, T. ; Yamashita, H. ; Yuki, F. ; Baba, T. ; Koyama, A. ; Sonehara, M.
Author_Institution
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fYear
2003
fDate
12-14 June 2003
Firstpage
57
Lastpage
60
Abstract
We developed a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Our unique approach of treating a sequential 16-bit incoming data as one unit achieved a fully digital "eye-tracking" DR circuit. Fabricated by 0.18-/spl mu/m SiGe-BiCMOS technology, the area of the DR circuit is 0.02-mm/sup 2//ch and its power consumption is 50 mW/ch at 1.8 V. The measured jitter tolerance at 2.5 Gb/s is 0.7 UI p-p, which satisfies the jitter specifications for the SFI-5.
Keywords
BiCMOS digital integrated circuits; Ge-Si alloys; power consumption; semiconductor materials; 0.18 micron; 1.8 V; 2.5 Gbit/s; SiGe; SiGe-BiCMOS technology; data recovery circuit; eye tracking method; jitter tolerance; power consumption; Area measurement; Circuits; Clocks; Energy consumption; Jitter; Laboratories; Optical buffering; Optical devices; Power measurement; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-034-8
Type
conf
DOI
10.1109/VLSIC.2003.1221160
Filename
1221160
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