Title :
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector
Author :
Nosaka, H. ; Sano, E. ; Ishii, K. ; Ida, M. ; Kurishima, K. ; Yamahata, S. ; Shibata, T.
Author_Institution :
NTT Photonics Lab., NTT Corp., Tokyo, Japan
Abstract :
We present a 40-Gbit/s-class clock and data recovery (CDR) circuit with a new lock detector. The lock detector operates robustly with a linear-type phase detector. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40, 43, and 45-Gbit/s PRBS with a length of 2/sup 31/-1. By attaching a frequency search and phase control (FSPC) circuit to the chip, the CDR circuit pulls in throughout a 39-45 Gbit/s range. The fabricated IC dissipates 1.89 W at a supply voltage of -4.5V.
Keywords :
clocks; digital integrated circuits; phase detectors; synchronisation; -4.5 V; 1.89 W; 39 to 45 Gbit/s; InP-InGaAs HBT; data recovery circuit; heterojunction bipolar transistor; multidata rate clock; phase detector; robust lock detector; Circuits; Clocks; Detectors; Error-free operation; Frequency; Indium gallium arsenide; Indium phosphide; Joining processes; Phase detection; Robustness;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221161
