A fourth order continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers

Author

Esfahani, F. ; Basedau, P. ; Ryter, R. ; Becker, R.

Author_Institution

Philips Semicond. AG, Zurich, Switzerland

fYear

2003

fDate

12-14 June 2003

Firstpage

75

Lastpage

78

Abstract

A low-power fourth order continuous-time complex /spl Sigma//spl Delta/ ADC has been designed and fabricated for low-IF (LIF) GSM and EDGE receivers in a 0.25 /spl mu/m CMOS technology. This ADC has a bandwidth of 270 kHz centered around-100 kHz. The dynamic range (DNR) is 82 dB at a sampling rate of 13 MHz even though the digital decimation filter and other blocks are active on the chip. The power consumption is 4.6 mW at 2 V supply. To our knowledge this ADC has the best performance, which has been reported so far with a complex /spl Sigma//spl Delta/ ADC for LIF mode GSM and EDGE receivers.

Keywords

CMOS integrated circuits; band-pass filters; cellular radio; power consumption; radio receivers; sigma-delta modulation; -100 kHz; 0.25 micron; 13 MHz; 2 V; 270 kHz; 4.6 mW; 82 dB; CMOS technology; analogue-digital conversion; bandwidth; digital decimation filter; dynamic range; global system for mobile communications receivers; low-IF GSM receivers; power consumption; sigma-delta ADC; Band pass filters; Bandwidth; CMOS technology; Delta-sigma modulation; Dynamic range; Energy consumption; Frequency; GSM; Hip; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-034-8

Type

conf

DOI

10.1109/VLSIC.2003.1221166

Filename

1221166