Title :
Double snapback phenomena in transient power-rail ESD clamp circuits for latch-up free concerns
Author :
Guangyi Lu ; Yuan Wang ; Xing Zhang
Author_Institution :
Key Lab. of Microelectron. Devices & Circuits (MoE), Peking Univ., Beijing, China
fDate :
June 29 2015-July 2 2015
Abstract :
Double snapback phenomena in transient power-rail ESD clamp circuits are reported in this paper. By properly sequencing different snapback mechanisms, the reported double snapback phenomena present latch-up free ESD protection schemes. Experiment results verify that both the first holding voltage (Vh1) and second holding current (Ih2) meet latch-up free criteria for the utilized 65-nm CMOS process. Besides, transient voltage waveforms in transmission line pulsing (TLP) tests are analyzed to fully understand the reported double snapback phenomena.
Keywords :
CMOS integrated circuits; electrostatic discharge; power electronics; transmission lines; CMOS process; double snapback phenomena; first holding voltage; latch-up free ESD protection schemes; second holding current; size 65 nm; snapback mechanisms; transient power-rail ESD clamp circuits; transient voltage waveforms; transmission line pulsing tests; Clamps; Electrostatic discharges; Latches; Logic gates; Simulation; Transient analysis;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the
Conference_Location :
Hsinchu
DOI :
10.1109/IPFA.2015.7224396
