Title :
A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM´s
Author :
Ohsawa, T. ; Higashi, T. ; Fujita, K. ; Ikehashi, T. ; Kajiyama, T. ; Fukuzumi, Y. ; Shino, T. ; Yamada, H. ; Nakajima, H. ; Minami, Y. ; Yamada, T. ; Inoh, K. ; Hamamoto, T.
Author_Institution :
SoC Res. & Dev. Center, Toshiba Corp., Yokohama, Japan
Abstract :
A 288 Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 /spl mu/m/sup 2/(7F/sup 2/ with F=0.175 /spl mu/m) which we named the floating body transistor cell (FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96 Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100 ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.
Keywords :
DRAM chips; integrated circuit design; silicon-on-insulator; transistors; 288 KB; 96 KB; DRAM memory cell; SOI; common mode noise; floating body transistor cell; temperature fluctuation; transistor gain cell; Circuit noise; Circuit testing; Fluctuations; Noise measurement; Performance gain; Random access memory; Semiconductor device measurement; Temperature sensors; Threshold voltage; Time measurement;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221171
