• DocumentCode
    1868866
  • Title

    2.5D/3D device package level defect localization with the use of multiple curve tracings and repeated thermal emission analyses

  • Author

    Lee Lan Yin ; Chua Kok Keng ; Tan, Grace

  • Author_Institution
    Xilinx Asia Pacific, Singapore, Singapore
  • fYear
    2015
  • fDate
    June 29 2015-July 2 2015
  • Firstpage
    287
  • Lastpage
    290
  • Abstract
    Defect localization becomes ever more challenging for low leakage failures especially with the dies stacking. More fault localization tools and innovative analytical techniques and procedures will be required during failure analysis. In this case, a very low leakage failure was reported in Xilinx 28nm technology node 2.5D SSIT package device. Low leakage was confirmed however both OBIRCH and thermal emission analyses could not detect any hotspot from the front side of the package. TDR analysis also showed no obvious anomaly as compared to a reference unit. Unit was flipped to the solder-ball side and repeated thermal emission successfully detected one big diffused emission hotspot in the package substrate region. Upon removing every substrate metal layer, curve trace verification was repeated to ensure confirm the leakage failure; while thermal emission analysis was repetitively performed and the emission hotspot tends to become more solid. Further package delayering revealed the dendrite defect located exactly at the thermal emission hotspot location along the long substrate metal trace, shorted to the neighboring ground plane and caused the reported failure.
  • Keywords
    fault location; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; solders; thermal analysis; three-dimensional integrated circuits; 2.5D SSIT package device; 2.5D device package level; 3D device package level; OBIRCH; TDR analysis; Xilinx technology node; curve trace verification; curve tracings; defect localization; die stacking; fault localization tools; leakage failures; package delayering; package substrate region; size 28 nm; solder-ball side; substrate metal layer; substrate metal trace; thermal emission analysis; thermal emission hotspot location; Electronic packaging thermal management; Failure analysis; Metals; Silicon; Solids; Substrates; Thermal analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the
  • Conference_Location
    Hsinchu
  • Type

    conf

  • DOI
    10.1109/IPFA.2015.7224399
  • Filename
    7224399