A memory efficient array architecture for full-search block matching algorithm

Author

Moshnyaga, Vasily G. ; Tamaru, Keikichi

Author_Institution

Dept. of Electron., Kyoto Univ., Japan

Volume

5

fYear

1997

fDate

21-24 Apr 1997

Firstpage

4109

Abstract

This paper proposes a novel array architecture for full-search block matching motion estimation. The design efforts are focused on transforming the array computation in a way that minimizes the memory and I/O costs while satisfying the highest throughput requirements. Compared with the existing architectures, this one ensures feasible solutions for the HDTV picture format with twice lower memory requirements, minimal I/O pin count and 100% processor utilization. The architecture features regular and simple interconnects and is quite suitable for VLSI implementation

Keywords

VLSI; digital signal processing chips; distributed memory systems; high definition television; image matching; integrated memory circuits; motion estimation; parallel architectures; video coding; HDTV picture format; I/O costs; VLSI implementation; array computation; block matching motion estimation; design; distributed memory architecture; full-search block matching algorithm; memory costs minimisation; memory efficient array architecture; minimal I/O pin count; processor utilization; regular interconnects; throughput requirements; video coding; Bandwidth; Computer architecture; HDTV; Memory architecture; Motion estimation; Parallel processing; Random access memory; Registers; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on

Conference_Location

Munich

ISSN

1520-6149

Print_ISBN

0-8186-7919-0

Type

conf

DOI

10.1109/ICASSP.1997.604850

Filename

604850