Title :
A 10-mW 3.6-Gbps I/O transmitter
Author :
Hatamkhani, H. ; Koon-Lun Jackie Wong ; Drost, R. ; Chih-Kong Ken Yang
Author_Institution :
California Univ., Los Angeles, CA, USA
Abstract :
This paper describes a low-power self-terminated transmitter. A novel architecture is proposed to perform impedance matching and channel equalization with low power consumption. The test chip is fabricated using 0.18-/spl mu/m digital CMOS process with 1.8-V supply. The transmitter operates at 3.6 Gbps and consumes 9.66 mW. The total transmitter area is 0.072 mm/sup 2/.
Keywords :
CMOS digital integrated circuits; impedance matching; integrated circuit design; transmitters; 0.18 micron; 1.8 V; 10 mW; 9.66 mW; I/O transmitter; channel equalization; digital CMOS; impedance matching; self-terminated transmitter; Clocks; Energy consumption; Filters; Impedance matching; Low voltage; Multiplexing; Power dissipation; Power supplies; Signal design; Transmitters;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221172
