DocumentCode
1868905
Title
A 27-mW 3.6-Gb/s I/O transceiver
Author
Wong, K.L.J. ; Mansuri, M. ; Hatamkhani, H. ; Yang, C.-K.K.Y.
Author_Institution
California Univ., Los Angeles, CA, USA
fYear
2003
fDate
12-14 June 2003
Firstpage
99
Lastpage
102
Abstract
This paper describes a 3.6-Gbps 27-mW transceiver for chip-to-chip applications. A novel data receiving and timing recovery technique are presented with very low power penalties while maintaining high signal integrity. The input comparator filters noise with built-in bandwidth control and digital offset compensation while consuming 300 uW. Static phase offset introduced onto the charge-pump permits phase recovery with no additional power. The entire design occupies 0.2 mm/sup 2/ in a 0.18-/spl mu/m 1.8-V CMOS technology.
Keywords
CMOS integrated circuits; circuit noise; comparators (circuits); synchronisation; transceivers; 1.8 V; 27 mW; CMOS technology; built-in bandwidth control; charge-pump; chip-chip application; comparator filters noise; data receiving; digital offset compensation; input output transceiver; phase recovery; signal integrity; static phase offset; timing recovery; Bandwidth; CMOS technology; Clocks; Energy consumption; Filters; Phase locked loops; Timing; Transceivers; Transmitters; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-034-8
Type
conf
DOI
10.1109/VLSIC.2003.1221173
Filename
1221173
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