DocumentCode
1868932
Title
Superpipelined adder designs
Author
Swartzlander, Earl E.
fYear
1993
fDate
3-6 May 1993
Firstpage
1841
Lastpage
1844
Keywords
Clocks; Delay; High performance computing; Inverters; Logic design; Logic gates; Pipeline processing; Signal processing; Throughput; Vector processors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
IEEE
Print_ISBN
0-7803-1281-3
Type
conf
Filename
693030
Link To Document