Real-time Software Modelling using Statecharts and Timed Automata Approaches

Author

Naughton, M. ; McGrath, John ; Heffernan, Donal

Author_Institution

Centre for Telecoms Value-chain Driven Res., Limerick Univ.

fYear

2006

fDate

28-30 June 2006

Firstpage

129

Lastpage

134

Abstract

Statecharts are commonly used in the specification of reactive systems. They are useful in introducing modular and hierarchical features to classical finite-state machines (FSMs). UML statecharts are gaining popularity for the modelling of real-time embedded software. However, UML statecharts are weak in their support for absolute time and they do not formally support verification methods. Timed automata models, on the other hand, are rich in support of real-time modelling and support formal verification solutions. In this paper the statechart method and the timed automata method are compared. A case study model for an ATM output buffer switch is developed and the models are presented

Keywords

Unified Modeling Language; asynchronous transfer mode; buffer storage; embedded systems; finite state machines; formal verification; packet switching; ATM output buffer switch; FSM; UML statechart; Unified Modeling Language; asynchronous transfer mode; classical finite-state machine; formal verification method; hierarchical feature; modular feature; reactive system; real-time embedded software modelling; timed automata model; ATM; Statecharts; UML; modelling; timed automata;

fLanguage

English

Publisher

iet

Conference_Titel

Irish Signals and Systems Conference, 2006. IET

Conference_Location

Dublin

Print_ISBN

0-86341-665-9

Type

conf

Filename

4123882