Title :
Software prefetching for software pipelined loops
Author :
Sánchez, F. Jesüs ; González, Antonio
Author_Institution :
Dept. d´´Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
The paper investigates the interaction between software pipelining and different software prefetching techniques for VLIW machines. It is shown that processor stalls due to memory dependencies have a great impact into execution time. A novel heuristic is proposed and it is show to outperform previous proposals
Keywords :
cache storage; instruction sets; parallel machines; pipeline processing; processor scheduling; VLIW machines; execution time; heuristic; memory dependence; processor stalls; software pipelined loops; software prefetching; Argon; Computer architecture; Degradation; Delay; Pipeline processing; Prefetching; Processor scheduling; Proposals; Registers; VLIW;
Conference_Titel :
System Sciences, 1998., Proceedings of the Thirty-First Hawaii International Conference on
Conference_Location :
Kohala Coast, HI
Print_ISBN :
0-8186-8255-8
DOI :
10.1109/HICSS.1998.649285
