Title :
A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process
Author :
McAdams, H. ; Acklin, R. ; Blake, T. ; Fong, J. ; Liu, D. ; Madan, S. ; Moise, T. ; Natarajan, S. ; Qian, N. ; Qui, Y. ; Roscher, J. ; Seshadri, A. ; Summerfelt, S. ; Du, X. ; Eliason, J. ; Kraus, W. ; Lanham, R. ; Li, F. ; Pietrzyk, C. ; Rickes, J.
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic process. Address access time for the memory is less than 30 ns while consuming 0.57 mW/MHz at 1.37 V. An eFRAM density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.
Keywords :
ferroelectric storage; masks; modules; random-access storage; 1.3 V; 130 nm; 64 MB; FRAM; address access time; capacitor size; cell size; ferroelectric module; ferroelectric random access memory; Capacitors; Decoding; Driver circuits; Electrodes; Ferroelectric films; Ferroelectric materials; Logic; Nonvolatile memory; Polarization; Random access memory;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221194
