A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis

Author

Verma, S. ; Junfeng Xu ; Lee, T.H.

Author_Institution

Center for Integrated Syst., Stanford Univ., CA, USA

fYear

2003

fDate

12-14 June 2003

Firstpage

189

Lastpage

192

Abstract

A frequency-synthesis technique which extracts the N/sup th/ harmonic from an N-stage oscillator is presented. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled, single-ended three-stage ring oscillators has been fabricated in 0.24 /spl mu/m CMOS, designed to work in the 902-928 MHz ISM band (US and Canada). It provides two outputs: one at the normal operating frequency of the oscillator, and another at three times that frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.

Keywords

CMOS integrated circuits; frequency synthesizers; harmonic oscillators (circuits); phase locked loops; 0.24 micron; 1.3 V; 210 muA; 902 to 928 MHz; CMOS; low power frequency synthesis; three stage coupled ring oscillator; Energy consumption; Frequency conversion; Frequency locked loops; Frequency synthesizers; Integrated circuit synthesis; Low voltage; Power harmonic filters; Radio transceivers; Ring oscillators; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-034-8

Type

conf

DOI

10.1109/VLSIC.2003.1221199

Filename

1221199