Title :
Fast and reliable charge-trap non-volatile memories using low thermal budget processes in monolithic 3DIC application
Author :
Wen-Hsien Huang ; Chih-Chao Yang ; Tung-Ying Hsieh ; Hsing-Hsiang Wang ; Chang-Hong Shen ; Jia-Min Shieh
Author_Institution :
Nat. Nano Device Labs., Hsinchu, Taiwan
fDate :
June 29 2015-July 2 2015
Abstract :
We developed a low thermal budget NVM to exhibit a faster operation speed (1 μs) and a lower operation voltage (+9 V) with reliable retention and endurance. Accordingly, the NVM fabrication processes reduce the power consumption, and are compatible with the CMOS technology, facilitating the realization of monolithic SRAM/NVM in the future.
Keywords :
CMOS memory circuits; annealing; chemical vapour deposition; electron traps; hole traps; integrated circuit reliability; random-access storage; three-dimensional integrated circuits; CMOS technology; charge trap nonvolatile memories; low thermal budget NVM; low thermal budget processes; monolithic 3DIC application; monolithic SRAM; Grain size; Logic gates; Nonvolatile memory; Photonic band gap; Rough surfaces; Silicon; Surface roughness;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2015 IEEE 22nd International Symposium on the
Conference_Location :
Hsinchu
DOI :
10.1109/IPFA.2015.7224424
