• DocumentCode
    1869636
  • Title

    Transform Dual Transition Timed Petri Net into Timed Automaton for Model Checking with UPPAAL

  • Author

    Luo, Yigui

  • Author_Institution
    Embedded Syst. Lab., Tongji Univ., Shanghai, China
  • fYear
    2010
  • fDate
    10-12 Dec. 2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper presents the transformation of dual transition timed Petri Net (DTTPN) into timed automaton for model checking embedded system described in DTTPN which can model real-time embedded system in both control and data domain on different design phases. This paper proposes to transform a DTTPN model subnet into automaton, and then combine these concurrent subnets into whole one. For each DTTPN subnet, a time transition system is defined as active set net, which is bisimulated with this DTTPN subnet. Again by bisimulating this active set net, active set timed automaton is defined. Based on this active set timed automaton, model checking with UPPAAL can be carried out on events collision, resource constraints and so on. This paper gives the details of the transformation method, and model checking examples.
  • Keywords
    Petri nets; automata theory; formal verification; DTTPN subnet; UPPAAL; dual transition timed Petri net; model checking embedded system; time transition system; timed automata; Automata; Computational modeling; Data models; Embedded systems; Fires; Firing; Transforms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computational Intelligence and Software Engineering (CiSE), 2010 International Conference on
  • Conference_Location
    Wuhan
  • Print_ISBN
    978-1-4244-5391-7
  • Electronic_ISBN
    978-1-4244-5392-4
  • Type

    conf

  • DOI
    10.1109/CISE.2010.5676750
  • Filename
    5676750