Title :
A process variation compensating technique for sub-90 nm dynamic circuits
Author :
Kim, C.H. ; Roy, K. ; Hsu, S. ; Alvandpour, A. ; Krishnamurthy, R.K. ; Borkar, S.
Author_Institution :
Dept. of ECE, Purdue Univ., West Lafayette, IN, USA
Abstract :
A process variation compensating technique for dynamic circuits is described for sub-90 nm technologies where leakage variation is severe. A keeper whose effective strength is optimally programmable based on die leakage enables 10% faster performance, 35% reduction in delay variation, and 5x reduction in robustness failing dies over conventional static keeper design in 90 nm dual-V/sub t/ CMOS.
Keywords :
CMOS integrated circuits; integrated circuit design; 90 nm; conventional static keeper design; die leakage; dual-V/sub t/ CMOS; dynamic circuits; process variation compensating method; robustness; CMOS process; CMOS technology; Circuits; Degradation; Delay effects; MOS devices; Noise robustness; Performance loss; Robust control; Testing;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221203
