A high-speed 128 Kbit MRAM core for future universal memory applications

Author

Bette, A. ; DeBrosse, J. ; Gogl, D. ; Hoenigschmid, H. ; Robertazzi, R. ; Arndt, C. ; Braun, D. ; Casarotto, D. ; Havreluk, R. ; Lammers, S. ; Obermaier, W. ; Reohr, W. ; Viehmann, H. ; Gallagher, W.J. ; Muller, G.

Author_Institution

MRAM Dev. Alliance, Infineon Technol., Hopewell Junction, NY, USA

fYear

2003

fDate

12-14 June 2003

Firstpage

217

Lastpage

220

Abstract

A 128 Kb MRAM (Magnetic Random Access Memory) test chip has been fabricated utilizing for the first time a 0.18 /spl mu/m, VDD=1.8 V, logic process technology with Cu backend of line. The presented design uses a 1.4 /spl mu/m/sup 2/ ITIMTJ (1-Transistor/1-Magnetic Tunnel Junction) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5 ns random array read access time and random write operations with <5 ns write pulse width.

Keywords

copper; extrapolation; magnetic core stores; magnetic storage; magnetic tunnelling; random-access storage; 0.18 micron; 1-transistor-1-magnetic tunnel junction cell; 1.8 V; 128 KB; 5 ns; Cu; Cu backend; MRAM core test chip; complementary reference cells; extrapolations; logic process; magnetic random access memory; random array read access time; random write operations; symmetrical high-speed sensing architecture; universal memory applications; write pulse width; Circuit testing; Extrapolation; Logic devices; Logic testing; Magnetic cores; Pulse circuits; Pulse measurements; Random access memory; Semiconductor device measurement; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-034-8

Type

conf

DOI

10.1109/VLSIC.2003.1221207

Filename

1221207