• DocumentCode
    1869814
  • Title

    Low 1/f noise and DC offset RF mixer for direct conversion receiver using parasitic vertical NPN bipolar transistor in deep n-well CMOS technology

  • Author

    Ilku Nam ; Young Jin Kim ; Kwyro Lee

  • Author_Institution
    Dept. of EECS, KAIST, Daejeon, South Korea
  • fYear
    2003
  • fDate
    12-14 June 2003
  • Firstpage
    223
  • Lastpage
    226
  • Abstract
    RF characteristics of the parasitic vertical NPN bipolar junction transistor (BJT) available in 0.18 /spl mu/m foundry deep n-well CMOS technology are reported for the first time. The experimental results show that the vertical NPN BJT has about 20 of current gain, 7 V of collector-emitter breakdown voltage, 20 V of collector-base breakdown voltage, 40 V of early voltage, 2.3 GHz of cutoff frequency, and 3.5 GHz of maximum oscillation frequency at room temperature. The corner frequency of flicker noise is lower than 4 kHz at 0.5 mA. Double balanced RF mixer using V-NPN shows almost free 1/f noise as well as order of magnitude smaller DC offset with other characteristics comparable with CMOS one and 12 dB flat up to the cutoff frequency, opening the possibility of high performance direct conversion receiver implementation in CMOS technology.
  • Keywords
    1/f noise; CMOS integrated circuits; bipolar transistors; flicker noise; mixers (circuits); semiconductor device breakdown; semiconductor device noise; 0.18 micron; 0.5 mA; 1/f noise; 12 dB; 2.3 GHz; 20 V; 293 to 298 K; 3.5 GHz; 4 kHz; 40 V; 7 V; DC offset RF mixer; bipolar junction transistor; collector-base breakdown voltage; collector-emitter breakdown voltage; conversion receiver; cutoff frequency; deep n well CMOS; double balanced RF mixer; flicker noise; oscillation frequency; parasitic vertical NPN bipolar transistor; room temperature; 1f noise; Bipolar transistors; CMOS process; CMOS technology; Circuits; Costs; Cutoff frequency; Foundries; Radio frequency; Receivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    4-89114-034-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.2003.1221209
  • Filename
    1221209