Title :
A 90 nm 1 GHz 22 mW 16/spl times/16-bit 2´s complement multiplier for wireless baseband
Author :
Zeydel, B.R. ; Oklobdzija, V.G. ; Mathew, S. ; Krishnamurthy, R.K. ; Borkar, S.
Author_Institution :
Dept. of ECE, California Univ., Davis, CA, USA
Abstract :
This paper describes a static 16/spl times/16-bit 2´s complement wireless baseband multiplier testchip in 1.2 V, 90 nm dual-Vt CMOS technology. One-hot Booth encoding, sum/delay difference optimized 3:2 compressor tree, and signal-profile optimized final adder schemes are employed to achieve 1 GHz, 22 mW operation at 1.2 V, scalable to 500 MHz, 3 mW at 0.8 V.
Keywords :
CMOS integrated circuits; adders; encoding; frequency multipliers; integrated circuit testing; 0.8 V; 1 GHz; 1.2 V; 500 MHz; 90 nm; CMOS; compressor tree; hot Booth encoding; signal-profile optimized adder; wireless baseband multiplier; Adders; Baseband; CMOS technology; Circuit topology; Clocks; Delay; Encoding; Latches; Testing; Wiring;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221212
