Title :
A 90 nm 6.5 GHz 256/spl times/64 b dual supply register file with split decoder scheme
Author :
Hsu, S. ; Chatterjee, B. ; Sachdev, M. ; Alvandpour, A. ; Krishnamurthy, R.K. ; Borkar, S.
Author_Institution :
Intel Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
This paper describes a 256/spl times/64 b 2-read, 1-write ported static register file for 6.5 GHz operation in 1.2 V, 90 nm CMOS. Read/write select drivers and decoder use 0.9 V lower supply to reduce total energy by 23%. Local/global bitlines use a leakage-tolerant split-decoder scheme with conditional precharge to achieve 65% (90%) higher DC robustness compared to conventional static (dynamic) bitline scheme.
Keywords :
codecs; computer architecture; decoding; digital arithmetic; logic design; 6.5 GHz; 90 nm; CMOS; DC robustness; dual supply register; precharge; split decoder; Artificial intelligence; Circuits; Decoding; Registers; Robustness; Very large scale integration;
Conference_Titel :
VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-034-8
DOI :
10.1109/VLSIC.2003.1221213
